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features ? high performance, low power avr ? 32 uc 32-bit microcontroller ? compact single-cycle risc instruction set including dsp instruction set ? read-modify-write instructions and atomic bit manipulation ? up to 66 mhz clock frequency with 1.24 dmips/mhz ? memory protection unit ? multi-hierarchy bus system ? high-performance data transfers on separate buses for increased performance ? 15 peripheral dma channels for automatic data transfer ? internal high-speed flash ? 512k bytes, 256k bytes, 128k bytes versions ? single cycle access up to 30 mhz ? prefetch buffer optimizing instru ction execution at maximum speed ? 1ms page programming time and 2ms full-chip erase time ? 100,000 write cycles, 10-year data retention capability ? flash security locks and us er defined configuration area ? internal high-speed sram, si ngle-cycle access at full speed ? 64k bytes (512kb and 256kb flash), 32k bytes (128kb flash) ? external memory interface on at32uc3a0 derivatives ? sdram / sram compatible memory bus (16-bit data and 24-bit address buses) ? interrupt controller ? autovectored low latency interrupt service with programmable priority ? system functions ? power and clock manager including inte rnal rc clock and one 32khz oscillator ? two multipurpose oscillators and two phase-lock-loop (pll) ? watchdog timer, real-time clock timer ? universal serial bus (usb) ? device 2.0 full speed and on-the-go (otg) low speed and full speed ? flexible end-point configuration and management with dedicated dma channels ? on-chip transceivers including pull-ups ? ethernet mac 10/100 mbps interface ? 802.3 ethernet me dia access controller ? supports media independent interf ace (mii) and reduced mii (rmii) ? one three-channel 16-b it timer/counter (tc) ? three external clock inputs, pwm, capture and various counting capabilities ? one 7-channel 16-bit pulse width modulation controller (pwm) ? four universal synchronous/asynchro nous receiver/transmitters (usart) ? independant baudrate generator, su pport for irda and iso7816 interfaces ? support for hardware handshaki ng, rs485 interfaces and modem line ? two master/slave serial peripheral inte rfaces (spi) with chip select signals ? one synchronous serial protocol controller ? supports i2s and generic frame-based protocols ? one master/slave two-wire interfa ce (twi), 400kbit/s i2c-compatible ? one 8-channel 10-bit anal og-to-digital converter ? on-chip debug system (jtag interface) ? nexus class 2+, runtime control, no n-intrusive data and program trace ? 100-pin tqfp (69 gpio pins), 144-pin lqfp (109 gpio pins) ? 5v input tolerant i/os ? single 3.3v power supply 32058as?avr32?03/07 avr ? 32 32-bit microcontroller AT32UC3A0512 at32uc3a0256 at32uc3a0128 at32uc3a1512 at32uc3a1256 at32uc3a1128 preliminary summary
2 32058as?avr32?03/07 1. description the at32uc3a is a complete system-on-chip microcontroller based on the avr32 uc risc processor running at frequencies up to 66 mhz. avr32 uc is a high-performance 32-bit risc microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on low power consumption, high code density and high performance. the processor implements a memory protection unit (mpu) and a fast and flexible interrupt con- troller for supporting modern operating systems and real-time operating systems. higher computation capabilities ar e achievable using a rich set of dsp instructions. the at32uc3a incorporates on-chip flash and sram memories for secure and fast access. for applications requiring additional memory, an external memory interface is provided on at32uc3a0 derivatives. the peripheral direct memory access controller enables data transfers between peripherals and memories without processor involvement. pdca drastically reduces processing overhead when transferring continuous and large data streams between modules within the mcu. the powermanager improves design flexibility and security: the on-chip brown-out detector monitors the power supply, the cpu runs from t he on-chip rc oscillator or from one of external oscillator sources, a real-time clock and its associated timer keeps track of the time. the timer/counter includes three identical 16- bit timer/counter channels. each channel can be independently programmed to perform frequency measurement, event counting, interval mea- surement, pulse generation, delay timing and pulse width modulation. the pwm modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. one pwm channel can trigger adc conversions for more accurate close loop control implementations. the at32uc3a also features many communication interfaces for communication intensive applications. in addition to standard serial interfaces like uart, spi or twi, other interfaces like flexible synchronous serial controller, usb and ethernet mac are available. the synchronous serial controller provides easy access to serial communication protocols and audio standards like i2s. the full-speed usb 2.0 device interface supports several usb classes at the same time thanks to the rich end-point configuration. t he on-the-go (otg) host interface allows device like a usb flash disk or a usb printer to be directly connected to the processor. the media-independent interface (mii) and reduced mii (rmii) 10/100 ethernet mac module provides on-chip solutions for network-connected devices. at32uc3a integrates a class 2+ nexus 2.0 on-chip debug (ocd) system, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control.
3 32058as?avr32?03/07 2. configuration summary the table below lists all at32uc3a memory and package configurations: device flash sram ext. bus interface package AT32UC3A0512 512 kbytes 64 kbytes yes 144 lead lqfp at32uc3a1512 512 kbytes 64 kbytes no 100 lead tqfp at32uc3a0256 256 kbytes 64 kbytes yes 144 lead lqfp at32uc3a1256 256 kbytes 64 kbytes no 100 lead tqfp at32uc3a0128 128 kbytes 32 kbytes yes 144 lead lqfp at32uc3a1128 128 kbytes 32 kbytes no 100 lead tqfp
4 32058as?avr32?03/07 3. blockdiagram figure 3-1. blockdiagram uc cpu nexus class 2+ ocd instr interface data interface timer/counter interrupt controller real time counter peripheral dma controller 512 kb flash hsb-pb bridge b hsb-pb bridge a s mm m m m s s s s s m external interrupt controller high speed bus matrix general purpose ios 64 kb sram general purpose ios pa pb pc px a[2..0] b[2..0] clk[2..0] extint[7..0] kps[7..0] nmi_n gclk[3..0] xin32 xout32 xin0 xout0 pa pb pc px reset_n external bus interface (sdram & static memory controller) cas ras sda10 sdck sdcke sdcs1 sdwe ncs[3..0] nrd nwait nwe0 data[15..0] usb interface dma id vbof vbus d- d+ ethernet mac dma 32 khz osc 115 khz rcosc osc0 pll0 pulse width modulation controller usart3 serial peripheral interface 0/1 two-wire interface pdc pdc pdc pdc rxd txd clk miso, mosi npcs[3..1] pwm[6..0] scl sda usart1 pdc rxd txd clk rts, cts dsr, dtr, dcd, ri usart0 usart2 pdc rxd txd clk rts, cts synchronous serial controller pdc tx_clock, tx_frame_sync rx_data tx_data rx_clock, rx_frame_sync analog to digital converter pdc ad[7..0] advref watchdog timer xin1 xout1 osc1 pll1 sck jtag interface mcko mdo[5..0] mseo[1..0] evti_n evto_n tck tdo tdi tms power manager reset controller addr[23..0] sleep controller clock controller clock generator col, crs, rxd[3..0], rx_clk, rx_dv, rx_er mdc, txd[3..0], tx_clk, tx_en, tx_er, speed mdio flash controller configuration registers bus memory protection unit pb pb hsb hsb nwe1 nwe3 pba pbb npcs0
5 32058as?avr32?03/07 3.1 processor and architecture 3.1.1 avr32 uc cpu ? 32-bit load/store avr32a risc architecture. ? 15 general-purpose 32-bit registers. ? 32-bit stack pointer, program counter and link register reside in register file. ? fully orthogonal instruction set. ? privileged and unprivileged modes enabling efficient and secure operating systems. ? innovative instruction set together with variable instruction length ensu ring industry leading code density. ? dsp extention with saturating arithmetic, and a wide variet y of multiply instructions. ? 3 stage pipeline allows one instruction per clock cycle for most instructions. ? byte, half-word, word and double word memory access. ? multiple interrupt priority levels. ? mpu allows for operating s ystems with memory protection. 3.1.2 debug and test system ? ieee1149.1 compliant jtag and boundary scan ? direct memory access and programming capabilities through jtag interface ? extensive on-chip debug features in compliance with ieee-isto 5001-2003 (nexus 2.0) class 2+ ? low-cost nanotrace supported. ? auxiliary port for high-speed trace information ? hardware support for 6 program and 2 data breakpoints ? unlimited number of softw are breakpoints supported ? advanced program, data, ownership, and watchpoint trace supported 3.1.3 peripheral dma controller ? transfers from/to peripheral to/from any memory space without interven tion of the processor. ? next pointer support, forbids strong real -time constraints on buffer management. ? fifteen channels ? two for each usart ? two for each serial synchronous controller ? two for each serial peripheral interface ? one for each adc ? two for each twi interface 3.1.4 bus system ? high speed bus (hsb) matrix with 6 masters and 6 slaves handled ? handles requests from the cpu data fetch, cpu instruction fetch, pdca, usbb, ethernet controller, cpu sab, and to inte rnal flash, internal sram, peri pheral bus a, peripheral bus b, ebi. ? round-robin arbitration (three modes supported: no default master, last accessed default master, fixed default master) ? burst breaking with slot cycle limit ? one address decoder provided per master
6 32058as?avr32?03/07 ? peripheral bus a able to run on at divided bus speeds compared to the high speed bus figure 3-1 gives an overview of the bus system. all modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the power manager. the figure identifies the number of master and slave interfaces of each module connected to the high speed bus, and which dma controller is connected to which peripheral.
7 32058as?avr32?03/07 4. signals description the following table gives details on the signal name classified by peripheral the signals are multiplexed with gpio pins as described in ?peripheral multiplexing on i/o lines? on page 25 . table 4-1. signal description list signal name function type active level comments power vddsys power supply for pll and adc power 1.65 to 1.95 v vddcore core power supply power 1.65 to 1.95 v vddio i/o power supply power 3.0 to 3.6v vddana analog power supply power 3.0 to 3.6v vddin voltage regulator input supply power 3.0 to 3.6v vddout voltage regulator output power output 1.65 to 1.95 v gndana analog ground ground gnd ground ground clocks, oscillators, and pll?s xin0, xin1, xin32 crystal 0, 1, 32 input analog xout0, xout1, xout32 crystal 0, 1, 32 output analog jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input auxiliary port - aux mcko trace data output clock output mdo0 - mdo5 trace data output output mseo0 - mseo1 trace frame control output evti_n event in output low evto_n event out output low
8 32058as?avr32?03/07 power manager - pm gclk0 - gclk3 generic clock pins output reset_n reset pin input low real time counter - rtc rtc_clock rtc clock output watchdog timer - wdt wdtext external watchdog pin output external interrup t controller - eic extint0 - extint7 external interrupt pins input kps0 - kps7 keypad scan pins output nmi_n non-maskable interrupt pin input low ethernet mac - macb col collision detect input crs carrier sense and data valid input mdc management data clock output mdio management data input/output i/o rxd0 - rxd3 receive data input rx_clk receive clock input rx_dv receive data valid input rx_er receive coding error input speed speed txd0 - txd3 transmit data output tx_clk transmit clock or reference clock output tx_en transmit enable output tx_er transmit coding error output external bus interface - hebi - uc3015 only addr0 - addr23 address bus output cas column signal output low table 4-1. signal description list signal name function type active level comments
9 32058as?avr32?03/07 data0 - data15 data bus i/o ncs0 - ncs3 chip select output low nrd read signal output low nwait external wait signal input low nwe0 write enable 0 output low nwe1 write enable 1 output low nwe3 write enable 3 output low ras row signal output low sda10 sdram address 10 line output sdck sdram clock output sdcke sdram clock enable output sdcs0-sdcs1 sdram chip select output low sdwe sdram write enable output low general purpose input/output 2 - gpioa, gpiob, gpioc p0 - p31 parallel i/o controller gpioa i/o p0 - p31 parallel i/o controller gpiob i/o p0 - p5 parallel i/o controller gpioc i/o p0 - p31 parallel i/o controller gpiox i/o serial peripheral in terface - spi0, spi1 miso master in slave out i/o mosi master out slave in i/o npcs0 - npcs3 spi peripheral chip select i/o low sck clock output synchronous serial controller - ssc rx_clock ssc receive clock i/o rx_data ssc receive data input rx_frame_sync ssc receive frame sync i/o tx_clock ssc transmit clock i/o table 4-1. signal description list signal name function type active level comments
10 32058as?avr32?03/07 tx_data ssc transmit data output tx_frame_sync ssc transmit frame sync i/o timer/counter - timer a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twi scl serial clock i/o sda serial data i/o universal synchronous asynchronous receiver transmitter - usart0, usart1, usart2, usart3 clk clock i/o cts clear to send input only usart0, usart1 dcd data carrier detect only usart0 dsr data set ready only usart0 dtr data terminal ready only usart0 ri ring indicator only usart0 rts request to send output only usart0, usart1 rxd receive data input rxdn inverted receive data input low txd transmit data output txdn inverted transmit data output low analog to digital converter - adc table 4-1. signal description list signal name function type active level comments
11 32058as?avr32?03/07 ad0 - ad7 analog input pins analog input advref analog positive reference voltage input analog input 2.6 to 3.6v pulse width modulator - pwm pwm0 - pwm6 pwm output pins output universal serial bus device - usb ddm usb device port data - analog ddp usb device port data + analog table 4-1. signal description list signal name function type active level comments
12 32058as?avr32?03/07 5. package and pinout the device pins are multiplexed with peripheral functions as described in ?peripheral multiplexing on i/o lines? on page 25 . figure 5-1. tqfp100 pinout 125 26 50 51 75 76 100 table 5-1. tqfp100 package pinout 1 pb20 26 pa 0 5 51 pa 2 1 76 pb08 2 pb21 27 pa 0 6 52 pa 2 2 77 pb09 3 pb22 28 pa 0 7 53 pa 2 3 78 pb10 4 vddio 29 pa 0 8 54 pa 2 4 79 vddio 5 gnd 30 pa 0 9 55 pa 2 5 80 gnd 6 pb23 31 pa 1 0 56 pa 2 6 81 pb11 7 pb24 32 n/c 57 pa 2 7 82 pb12 8 pb25 33 pa 1 1 58 pa 2 8 83 pa 2 9 9 pb26 34 vddcore 59 vddana 84 pa 3 1 10 pb27 35 gnd 60 advref 85 pc02 11 vddout 36 pa 1 2 61 gndana 86 pc03 12 vddin 37 pa 1 3 62 vddsys 87 pb13 13 gnd 38 vddcore 63 pc00 88 pb14 14 pb28 39 pa 1 4 64 pc01 89 tms 15 pb29 40 pa 1 5 65 pb00 90 tck 16 pb30 41 pa 1 6 66 pb01 91 tdo 17 pb31 42 pa 1 7 67 vddio 92 tdi 18 reset_n 43 pa 1 8 68 vddio 93 pc04 19 pa 0 0 44 pa 1 9 69 gnd 94 pc05 20 pa 0 1 45 pa 2 0 70 pb02 95 pb15 21 gnd 46 vbus 71 pb03 96 pb16 22 vddcore 47 vddio 72 pb04 97 vddcore
13 32058as?avr32?03/07 figure 5-2. lqfp144 pinout 23 pa 0 2 48 dm 73 pb05 98 pb17 24 pa 0 3 49 dp 74 pb06 99 pb18 25 pa 0 4 50 gnd 75 pb07 100 pb19 table 5-1. tqfp100 package pinout 136 37 72 73 108 109 144 table 5-2. vqfp144 package pinout 1 px00 37 gnd 73 pa 2 1 109 gnd 2 px01 38 px10 74 pa 2 2 110 px30 3 pb20 39 pa 0 5 75 pa 2 3 111 pb08 4 px02 40 px11 76 pa 2 4 112 px31 5 pb21 41 pa 0 6 77 pa 2 5 113 pb09 6 pb22 42 px12 78 pa 2 6 114 px32 7 vddio 43 pa 0 7 79 pa 2 7 115 pb10 8 gnd 44 px13 80 pa 2 8 116 vddio 9 pb23 45 pa 0 8 81 vddana 117 gnd 10 px03 46 px14 82 advref 118 px33 11 pb24 47 pa 0 9 83 gndana 119 pb11 12 px04 48 pa 1 0 84 vddsys 120 px34 13 pb25 49 n/c 85 pc00 121 pb12 14 pb26 50 pa 1 1 86 pc01 122 pa 2 9 15 pb27 51 vddcore 87 px20 123 pa 3 1 16 vddout 52 gnd 88 pb00 124 pc02 17 vddin 53 pa 1 2 89 px21 125 pc03 18 gnd 54 pa 1 3 90 pb01 126 pb13 19 pb28 55 vddcore 91 px22 127 pb14 20 pb29 56 pa 1 4 92 vddio 128 tms 21 pb30 57 pa 1 5 93 vddio 129 tck
14 32058as?avr32?03/07 22 pb31 58 pa 1 6 94 gnd 130 tdo 23 reset_n 59 px15 95 px23 131 tdi 24 px05 60 pa 1 7 96 pb02 132 pc04 25 pa 0 0 61 px16 97 px24 133 pc05 26 px06 62 pa 1 8 98 pb03 134 pb15 27 pa 0 1 63 px17 99 px25 135 px35 28 gnd 64 pa 1 9 100 pb04 136 pb16 29 vddcore 65 px18 101 px26 137 px36 30 pa 0 2 66 pa 2 0 102 pb05 138 vddcore 31 px07 67 px19 103 px27 139 pb17 32 pa 0 3 68 vbus 104 pb06 140 px37 33 px08 69 vddio 105 px28 141 pb18 34 pa 0 4 70 dm 106 pb07 142 px38 35 px09 71 dp 107 px29 143 pb19 36 vddio 72 gnd 108 vddio 144 px39 table 5-2. vqfp144 package pinout
15 32058as?avr32?03/07 6. power considerations 6.1 power supplies the at32uc3a has several types of power supply pins: ? vddio: powers i/o lines. voltage is 3.3v nominal. ? vddana: powers the adc voltage is 3.3v nominal. ? vddin: input voltage for the voltage regulator. voltage is 3.3v nominal. ? vddcore: powers the core, me mories, and peripherals. voltage is 1.8v nominal. ? vddsys: powers the pll and adc. voltage is 1.8v nominal. the ground pins gnd are common to vddcore and vddio. the ground pin for vddana and vddsys is gndana. see ?electrical characteristics? on page 33 for power consumption on the various supply pins. 6.2 voltage regulator the at32uc3a embeds a voltage regulator that converts from 3.3v to 1.8v with a load of up to 100 ma. the regulator takes its input voltage from vddin, and supplies the output voltage on vddout. vddout should be externally conn ected to the 1.8v domains to be powered. adequate output supply decoupling is mandator y for vddout to reduce ripple and avoid oscil- lations. the best way to achieve this is to use two capacitors in parallel: one external 470 pf (or 1 nf) npo capacitor should be connected between vddout and gnd as close to the chip as possible. one external 2.2 f (or 3.3 f) x7 r capacitor should be connected between vddout and gnd. adequate input supply decouplin g is mandatory for vddin in or der to improve startup stability and reduce source voltage drop. the input decoupling capacitor should be placed close to the chip. for example, two capacitors can be used in parallel: 100 nf npo and 4.7 f x7r.
16 32058as?avr32?03/07 7. i/o line considerations 7.1 jtag pins tms, tdi and tck have pull-up resistors. tdo is an output, driven at up to vddio, and has no pull-up resistor. 7.2 reset_n pin the reset_n pin is a schmitt input and integrates a permanent pull-up resistor to vddio. as the product integrat es a power-on reset cell, the reset_n pin can be left unconnected in case no reset from the system needs to be applied to the product. 7.3 twi pins when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. when used as gpio-pins or used for other peripherals, the pins have the same characteristics as pio pins. 7.4 gpio pins all the i/o lines integrate a programmable pull-up resistor . programming of this pull-up resistor is performed independently for each i/o line through the gpio controllers. after reset, i/o lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column ?reset state? of the gpio controller multiplexing tables.
17 32058as?avr32?03/07 8. memories 8.1 embedded memories ? internal high-speed flash ? 512 kbytes (AT32UC3A0512, at32uc3a1512) ? 256 kbytes (at32uc3a0256, at32uc3a1256) ? 128 kbytes (at32uc3a1128) - 0 wait state access at up to 30 mhz in worst case conditions - 1 wait state access at up to 60 mhz in worst case conditions - pipelined flash architecture, allowing burst re ads from sequential fl ash locations, hiding penalty of 1 wait state access - pipelined flash architecture typically reduce s the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation - 10 000 write cycles, 10-year data retention capability - 1 ms page programming time, 2 ms chip erase time - sector lock capabilities, boot loader protection, security bit - 64 fuses, 32 of which are preserved during chip erase - user page for data to be preserved during chip erase ? internal high-speed sram, singl e-cycle access at full speed ? 64 kbytes (AT32UC3A0512, at32uc3a0, at32uc3a0256 & at32uc3a1256) ? 32kbytes (at32uc3a1128) 8.2 physical memory map the system bus is implemented as a bus matrix . all system bus addresses are fixed, and they are never remapped in any way, not even in boot. note that avr32 uc cpu uses unsegmented translation, as described in the avr32 architecture manual. the 32-bit physical address space is mapped as follows: accesses to unused areas returns an error result to the master requesting such an access. the bus matrix has the several masters and slaves. each master has its own bus and its own decoder, thus allowing a different memory mapping per master. the master number in the table table 8-1. at32uc3a physical memory map start address size device AT32UC3A0512 at32uc3a1512 at32uc3a0256 at32uc3a1256 at32uc3a1128 0x0000_0000 64 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte embedded sram 0x8000_0000 512 kbyte 512 kbyte 256 kbyt e 256 kbyte 128 kbyte embedded flash 0xc000_0000 16 mbyte - 16 mbyte - - ebi sram cs0 0xc800_0000 16 mbyte - 16 mbyte - - ebi sram cs2 0xcc00_0000 16 mbyte - 16 mbyte - - ebi sram cs3 0xd000_0000 128 mbyte - 128 mbyte - - ebi sram/sdram cs1 0xe000_0000 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte usb configuration 0xfffe_0000 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte hsb-pb bridge a 0xffff_0000 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte hsb-pb bridge b
18 32058as?avr32?03/07 below can be used to index the hmatrix contro l registers. for example, mcfg0 is associated with the cpu data master interface. each slave has its own arbiter, thus allowing a different arbitration per slave. the slave number in the table below can be used to index the hmatrix control registers. for example, scfg3 is associated with the internal sram slave interface. table 8-2. high speed bus masters master 0 cpu data master 1 cpu instruction master 2 cpu sab master 3 pdca master 4 macb dma master 5 usbb dma table 8-3. high speed bus slaves slave 0 internal flash slave 1 hsb-pb bridge 0 slave 2 hsb-pb bridge 1 slave 3 internal sram slave slave 4 usbb slave slave 5 ebi
19 32058as?avr32?03/07 9. peripherals 9.1 peripheral address map table 9-1. peripheral address mapping address peripheral name bus 0xe0000000 usbb usbb slave interface - usbb hsb 0xfffe0000 usbb usbb configuration interface - usbb pbb 0xfffe1000 hmatrix hmatrix configuration interface - hmatrix pbb 0xfffe1400 flashc flash controller - flashc pbb 0xfffe1800 macb macb configuration interface - macb pbb 0xfffe1c00 smc static memory controller configuration interface - smc pbb 0xfffe2000 sdramc sdram controller configuration interface - sdramc pbb 0xffff0000 pdca peripheral dma interface - pdca pba 0xffff0800 intc interrupt controller interface - intc pba 0xffff0c00 pm power manager - pm pba 0xffff0d00 rtc real time clock - rtc pba 0xffff0d30 wdt watchdog timer - wdt pba 0xffff0d80 eic external interrupt controller - eic pba 0xffff1000 gpio general purpose io controller - gpio pba 0xffff1400 usart0 universal synchronous asynchronous receiver transmitter - usart0 pba 0xffff1800 usart1 universal synchronous asynchronous receiver transmitter - usart1 pba
20 32058as?avr32?03/07 9.2 interrupt r equest signal map the various modules may output interrupt request signals. these signals are routed to the inter- rupt controller (intc), described in a later c hapter. the interrupt controller supports up to 64 groups of interrupt requests. each group can have up to 32 interrupt request signals. all interrupt signals in the same group share the same autov ector address and priority level. refer to the documentation for the individual submodules for a description of the semantic of the different interrupt requests. the interrupt request signals are co nnected to the intc as follows. 0xffff1c00 usart2 universal synchronous asynchronous receiver transmitter - usart2 pba 0xffff2000 usart3 universal synchronous asynchronous receiver transmitter - usart3 pba 0xffff2400 spi0 serial peripheral interface - spi0 pba 0xffff2800 spi1 serial peripheral interface - spi1 pba 0xffff2c00 twi two wire interface - twi pba 0xffff3000 pwm pulse width modulation controller - pwm pba 0xffff3400 ssc synchronous serial controller - ssc pba 0xffff3800 tc timer/counter - tc pba 0xffff3c00 adc analog to digital converter - adc pba table 9-1. peripheral address mapping (continued) address peripheral name bus table 9-2. interrupt request signal map group line module signal 0 0 peripheral dma controller pdca 16
21 32058as?avr32?03/07 1 0 external interrupt controller eic 0 1 external interrupt controller eic 1 2 external interrupt controller eic 2 3 external interrupt controller eic 3 4 external interrupt controller eic 4 5 external interrupt controller eic 5 6 external interrupt controller eic 6 7 external interrupt controller eic 7 8 real time counter rtc 9 power manager pm 2 0 general purpose input/ou tput controller gpio 0 1 general purpose input/ou tput controller gpio 1 2 general purpose input/ou tput controller gpio 2 3 general purpose input/ou tput controller gpio 3 4 general purpose input/ou tput controller gpio 4 5 general purpose input/ou tput controller gpio 5 6 general purpose input/ou tput controller gpio 6 7 general purpose input/ou tput controller gpio 7 8 general purpose input/ou tput controller gpio 8 9 general purpose input/ou tput controller gpio 9 10 general purpose input/ output controller gpio 10 11 general purpose input/ output controller gpio 11 12 general purpose input/ output controller gpio 12 13 general purpose input/ output controller gpio 13 table 9-2. interrupt request signal map
22 32058as?avr32?03/07 3 0 peripheral dma controller pdca 0 1 peripheral dma controller pdca 1 2 peripheral dma controller pdca 2 3 peripheral dma controller pdca 3 4 peripheral dma controller pdca 4 5 peripheral dma controller pdca 5 6 peripheral dma controller pdca 6 7 peripheral dma controller pdca 7 8 peripheral dma controller pdca 8 9 peripheral dma controller pdca 9 10 peripheral dma controller pdca 10 11 peripheral dma controller pdca 11 12 peripheral dma controller pdca 12 13 peripheral dma controller pdca 13 14 peripheral dma controller pdca 14 4 0 flash controller flashc 50 universal synchronous asynchronous receiver transmitter usart0 60 universal synchronous asynchronous receiver transmitter usart1 70 universal synchronous asynchronous receiver transmitter usart2 80 universal synchronous asynchronous receiver transmitter usart3 9 0 serial peripheral interface spi0 10 0 serial peripheral interface spi1 11 0 two-wire interface twi 12 0 pulse width modulation controller pwm 13 0 synchronous serial controller ssc 14 0 timer/counter tc0 1 timer/counter tc1 2 timer/counter tc2 15 0 analog to digital converter adc 16 0 ethernet mac macb 17 0 usb interface usbb 18 0 sdram controller sdramc table 9-2. interrupt request signal map
23 32058as?avr32?03/07 9.3 clock connections 9.3.1 timer/counters each timer/counter channel can independently select an internal or external clock source for its counter: 9.3.2 usarts each usart can be connected to an internally divided clock: 9.3.3 spis each spi can be connected to an internally divided clock: 9.4 nexus ocd aux port connections if the ocd trace system is enabled, the trace system will take control over a number of pins, irre- spectively of the pio configuration. two different ocd trace pi n mappings are possible, table 9-3. timer/counter clock connections source name connection internal timer_clock1 clk_slow timer_clock2 clk_pba / 4 timer_clock3 clk_pba / 8 timer_clock4 clk_pba / 16 timer_clock5 clk_pba / 32 external xc0 see section 9.6 xc1 xc2 table 9-4. usart clock connections usart source name connection 0 internal clk_div clk_pba / 8 1 2 3 table 9-5. spi clock connections spi source name connection 0 internal clk_div clk_pba / 32 1
24 32058as?avr32?03/07 depending on the configuration of the ocd axs register. for details, see the avr32 uctechni- cal reference manual . 9.5 dma handshake signals the pdma and the peripheral modules communicate through a set of handshake signals. the following table defines the valid settings for t he peripheral identifier (pid) in the pdma periph- eral select register (psr). table 9-6. nexus ocd aux port connections pin axs=0 axs=1 evti_n pb19 pa08 mdo[5] pb16 pa27 mdo[4] pb14 pa26 mdo[3] pb13 pa25 mdo[2] pb12 pa24 mdo[1] pb11 pa23 mdo[0] pb10 pa22 evto_n pb20 pb20 mcko pb21 pa21 mseo[1] pb04 pa07 mseo[0] pb17 pa28 table 9-7. pdma handshake signals pid value peripheral module & direction 0adc 1 ssc - rx 2 usart0 - rx 3 usart1 - rx 4 usart2 - rx 5 usart3 - rx 6twi - rx 7 spi0 - rx 8 spi1 - rx 9 ssc - tx 10 usart0 - tx 11 usart1 - tx 12 usart2 - tx 13 usart3 - tx
25 32058as?avr32?03/07 9.6 peripheral multiplexing on i/o lines each gpio line can be assigned to one of 3 peripheral functions; a, b or c. the following table define how the i/o lines on the peripherals a, b and c are multiplexed by the gpio. 14 twi - tx 15 spi0 - tx 16 spi1 - tx table 9-7. pdma handshake signals pid value peripheral module & direction table 9-8. gpio controller func tion multiplexing tqfp100 vqfp144 pin gpio pin function a function b function c 19 25 pa00 gpio 0 usart0 - rxd tc - clk0 20 27 pa01 gpio 1 usart0 - txd tc - clk1 23 30 pa02 gpio 2 usart0 - clk tc - clk2 24 32 pa03 gpio 3 usart0 - rts eic - extint[4] 25 34 pa04 gpio 4 usart0 - cts eic - extint[5] 26 39 pa05 gpio 5 usart1 - rxd pwm - pwm[4] 27 41 pa06 gpio 6 usart1 - txd pwm - pwm[5] 28 43 pa07 gpio 7 usart1 - clk pm - gclk[0] spi0 - npcs[3] 29 45 pa08 gpio 8 usart1 - rts spi0 - npcs[1] eic - extint[7] 30 47 pa09 gpio 9 usart1 - cts spi0 - npcs[2] 31 48 pa10 gpio 10 spi0 - npcs[0] eic - extint[6] 33 50 pa11 gpio 11 spi0 - miso usbb - usb_id 36 53 pa12 gpio 12 spi0 - mosi usbb - usb_vbof 37 54 pa13 gpio 13 spi0 - sck 39 56 pa14 gpio 14 ssc - tx_frame_sync spi1 - npcs[0] ebi - ncs[0] 40 57 pa15 gpio 15 ssc - tx_clock spi1 - sck ebi - addr[20] 41 58 pa16 gpio 16 ssc - tx_data spi1 - mosi ebi - addr[21] 42 60 pa17 gpio 17 ssc - rx_data spi1 - miso ebi - addr[22] 43 62 pa18 gpio 18 ssc - rx_clock spi1 - npcs[1] 44 64 pa19 gpio 19 ssc - rx_frame_sync spi1 - npcs[2] 45 66 pa20 gpio 20 nmi spi1 - npcs[3] 51 73 pa21 gpio 21 adc - ad[0] eic - extint[0] 52 74 pa22 gpio 22 adc - ad[1] eic - extint[1] 53 75 pa23 gpio 23 adc - ad[2] eic - extint[2] 54 76 pa24 gpio 24 adc - ad[3] eic - extint[3] 55 77 pa25 gpio 25 adc - ad[4] eic - scan[0] ebi - ncs[0] 56 78 pa26 gpio 26 adc - ad[5] eic - scan[1] ebi - addr[20]
26 32058as?avr32?03/07 57 79 pa27 gpio 27 adc - ad[6] eic - scan[2] ebi - addr[21] 58 80 pa28 gpio 28 adc - ad[7] eic - scan[3] ebi - addr[22] 83 122 pa29 gpio 29 twi - sda usart2 - rts 84 123 pa30 gpio 30 twi - scl usart2 - cts 65 88 pb00 gpio 32 macb - tx_clk usart2 - rts 66 90 pb01 gpio 33 macb - tx_en usart2 - cts 70 96 pb02 gpio 34 macb - txd[0] 71 98 pb03 gpio 35 macb - txd[1] 72 100 pb04 gpio 36 macb - crs usart3 - clk ebi - ncs[3] 73 102 pb05 gpio 37 macb - rxd[0] 74 104 pb06 gpio 38 macb - rxd[1] 75 106 pb07 gpio 39 macb - rx_er 76 111 pb08 gpio 40 macb - mdc 77 113 pb09 gpio 41 macb - mdio 78 115 pb10 gpio 42 macb - txd[2] usart3 - rxd ebi - sdck 81 119 pb11 gpio 43 macb - txd[3] usart3 - txd ebi - sdcke 82 121 pb12 gpio 44 macb - tx_er tc - clk0 ebi - ras 87 126 pb13 gpio 45 macb - rxd[2] tc - clk1 ebi - cas 88 127 pb14 gpio 46 macb - rxd[3] tc - clk2 ebi - sdwe 95 134 pb15 gpio 47 macb - rx_dv 96 136 pb16 gpio 48 macb - col usbb - usb_id ebi - sda10 98 139 pb17 gpio 49 macb - rx_clk usbb - usb_vbof ebi - addr[23] 99 141 pb18 gpio 50 macb - speed adc - trigger pwm - pwm[6] 100 143 pb19 gpio 51 pwm - pwm[0] pm - gclk[0] eic - scan[4] 1 3 pb20 gpio 52 pwm - pwm[1] pm - gclk[1] eic - scan[5] 2 5 pb21 gpio 53 pwm - pwm[2] pm - gclk[2] eic - scan[6] 3 6 pb22 gpio 54 pwm - pwm[3] pm - gclk[3] eic - scan[7] 6 9 pb23 gpio 55 tc - a0 usart1 - dcd 7 11 pb24 gpio 56 tc - b0 usart1 - dsr 8 13 pb25 gpio 57 tc - a1 usart1 - dtr 9 14 pb26 gpio 58 tc - b1 usart1 - ri 10 15 pb27 gpio 59 tc - a2 pwm - pwm[4] 14 19 pb28 gpio 60 tc - b2 pwm - pwm[5] 15 20 pb29 gpio 61 usart2 - rxd pm - gclk[1] ebi - ncs[2] 16 21 pb30 gpio 62 usart2 - txd pm - gclk[2] ebi - sdcs 17 22 pb31 gpio 63 usart2 - clk pm - gclk[3] ebi - nwait 63 85 pc00 gpio 64 64 86 pc01 gpio 65 85 124 pc02 gpio 66 table 9-8. gpio controller func tion multiplexing
27 32058as?avr32?03/07 86 125 pc03 gpio 67 93 132 pc04 gpio 68 94 133 pc05 gpio 69 1 px00 gpio 100 ebi - data[10] 2 px01 gpio 99 ebi - data[9] 4 px02 gpio 98 ebi - data[8] 10 px03 gpio 97 ebi - data[7] 12 px04 gpio 96 ebi - data[6] 24 px05 gpio 95 ebi - data[5] 26 px06 gpio 94 ebi - data[4] 31 px07 gpio 93 ebi - data[3] 33 px08 gpio 92 ebi - data[2] 35 px09 gpio 91 ebi - data[1] 38 px10 gpio 90 ebi - data[0] 40 px11 gpio 109 ebi - nwe1 42 px12 gpio 108 ebi - nwe0 44 px13 gpio 107 ebi - nrd 46 px14 gpio 106 ebi - ncs[1] 59 px15 gpio 89 ebi - addr[19] 61 px16 gpio 88 ebi - addr[18] 63 px17 gpio 87 ebi - addr[17] 65 px18 gpio 86 ebi - addr[16] 67 px19 gpio 85 ebi - addr[15] 87 px20 gpio 84 ebi - addr[14] 89 px21 gpio 83 ebi - addr[13] 91 px22 gpio 82 ebi - addr[12] 95 px23 gpio 81 ebi - addr[11] 97 px24 gpio 80 ebi - addr[10] 99 px25 gpio 79 ebi - addr[9] 101 px26 gpio 78 ebi - addr[8] 103 px27 gpio 77 ebi - addr[7] 105 px28 gpio 76 ebi - addr[6] 107 px29 gpio 75 ebi - addr[5] 110 px30 gpio 74 ebi - addr[4] 112 px31 gpio 73 ebi - addr[3] 114 px32 gpio 72 ebi - addr[2] 118 px33 gpio 71 ebi - addr[1] 120 px34 gpio 70 ebi - addr[0] 135 px35 gpio 105 ebi - data[15] table 9-8. gpio controller func tion multiplexing
28 32058as?avr32?03/07 9.7 oscillator pinout the oscillators are not ma pped to the normal a,b or c functi ons and their muxings are controlled by registers in the power manager (pm). please refer to the power manager chapter for more information about this. 9.8 peripheral overview 9.8.1 external bus interface ? optimized for application memory space support ? integrates two external memory controllers: ? static memory controller ? sdram controller ? optimized external bus: ?16-bit data bus ? 24-bit address bus, up to 16-mbytes addressable ? optimized pin multiplexing to redu ce latencies on external memories ? 4 sram chip selects, 1sdram chip select: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2 ? static memory controller on ncs3 137 px36 gpio 104 ebi - data[14] 140 px37 gpio 103 ebi - data[13] 142 px38 gpio 102 ebi - data[12] 144 px39 gpio 101 ebi - data[11] table 9-8. gpio controller func tion multiplexing table 9-9. oscillator pinout tqfp100 pin vqfp144 pin pad oscillator pin 85 124 pc02 xin0 93 132 pc04 xin1 63 85 pc00 xin32 86 125 pc03 xout0 94 133 pc05 xout1 64 86 pc01 xout32
29 32058as?avr32?03/07 9.8.2 static memory controller ? 5 chip selects available ? 64-mbyte address space per chip select ? 8-, 16-bit data bus ? word, halfword, byte transfers ? byte write or by te select lines ? programmable setup, pulse and hold ti me for read signals per chip select ? programmable setup, pulse and hold time for write signals per chip select ? programmable data float time per chip select ? compliant with lcd module ? external wait request ? automatic switch to slow clock mode ? asynchronous read in page mode supporte d: page size ranges from 4 to 32 bytes 9.8.3 sdram controller ? numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path ? programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable ? energy-saving capabilities ? self-refresh, power-down and deep power modes supported ? supports mobile sdram devices ? error detection ? refresh error interrupt ? sdram power-up initialization by software ? cas latency of 1, 2, 3 supported ? auto precharge command not used 9.8.4 usb controller ? usb 2.0 compliant, full-/low-speed (f s/ls) and on-the-go (otg), 12 mbit/s ? 7 pipes/endpoints ? 960 bytes of embedded dual-port ram (dpram) for pipes/endpoints ? up to 2 memory banks per pipe/endpoint (not for control pipe/endpoint) ? flexible pipe/endpoint configuration and management with dedicated dma channels ? on-chip transceivers including pull-ups 9.8.5 serial peripheral interface ? supports communication with serial external devices ? four chip selects with extern al decoder support allow co mmunication with up to 15 peripherals ? serial memories, such as da taflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, l cd controllers, can controllers and sensors ? external co-processors
30 32058as?avr32?03/07 ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable da ta length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? very fast transfers supported ? transfers with baud rates up to mck ? the chip select line may be left active to speed up transfer s on the same device 9.8.6 two-wire interface ? high speed up to 400kbit/s ? compatibility with standard two-wire serial memory ? one, two or three bytes for slave address ? sequential read/write operations 9.8.7 usart ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in a synchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by-16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection ? optional manchester encoding ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? irda modulation and demodulation ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo 9.8.8 serial synchronous controller ? provides serial synchronous communication links used in audio and tel ecom applications (with codecs in master or slave modes, i2s, tdm buses, magnetic card reader, etc.) ? contains an independent receiver and transmitter and a common clock divider ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to st art automatically or on detection of different event on the frame sync signal ? receiver and transmitter include a data signal, a cloc k signal and a frame synchronization signal 9.8.9 timer counter ? three 16-bit timer counter channels ? wide range of functions including: ? frequency measurement
31 32058as?avr32?03/07 ? event counting ? interval measurement ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-conf igurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? two global registers that ac t on all three tc channels 9.8.10 pulse width modulation controller ? 7 channels, one 16-bit counter per channel ? common clock generator, providing thirteen different clocks ? a modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? independent channel programming ? independent enable disable commands ? independent clock ? independent period and duty cycle, with double bufferization ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform 9.8.11 ethernet 10/100 mac ? compatibility with ieee standard 802.3 ? 10 and 100 mbits per second data throughput capability ? full- and half-duplex operations ? mii or rmii interface to the physical layer ? register interface to address, da ta, status and control registers ? dma interface, operating as a ma ster on the memory controller ? interrupt generation to signal receive and transmit completion ? 28-byte transmit and 28-byte receive fifos ? automatic pad and crc genera tion on transmitted frames ? address checking logic to recognize four 48-bit addresses ? support promiscuous mode where all valid frames are copied to memory ? support physical layer management through mdio interface control of alarm and update time/calendar data
32 32058as?avr32?03/07 10. boot sequence this chapter summarizes the boot sequence of the at32uc3a. the behaviour after power-up is controlled by the power manager. for specific details, refer to section 13. ?power manager (pm)? on page 47 . 10.1 starting of clocks after power-up, the device will be held in a reset state by the power-on reset circuitry, until the power has stabilized throughout the device. once the power has stabilized, the device will use the internal rc oscilla tor as clock source. on system start-up, the plls are disabled. all clocks to all modules are running. no clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal rc oscillator. 10.2 fetching of initial instructions after reset has been released, the avr32 uc cpu starts fetching instructions from the reset address, which is 0x8000_0000. this address points to the first address in the internal flash. the code read from the internal flash is free to configure the system to use for example the plls, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals.
33 32058as?avr32?03/07 11. electrical characteristics 11.1 absolute maximum ratings* operating temperature.................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .......................................................... ....- 60c to +150c voltage on any pin except reset_n with respect to ground ............................-tbdv to v cc +tbdv voltage on reset_n wi th respect to grou nd-tbdv to +tbdv maximum operating voltage (vddcore, vddsys) .... 1.95v maximum operating voltage (vddio).............................. 3.6v dc current per i/o pin ............................................... tbd ma dc current v cc and gnd pins.................................. tbd ma
34 32058as?avr32?03/07 11.2 dc characteristics 11.3 power consumption the values in table 11-1 and table 11-2 on page 35 are measured values of power consump- tion with operating conditions as follows: ?v ddio = 3.3v ?v ddcore = v ddsys = 1.8v ?t a = 25 c ?i/os are inactive the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are certified for a junction temperature up to t j = 100c. symbol parameter condition min. typ. max. units v vddcor e dc supply core 1.65 1.95 v vddbu dc supply backup 1.65 1.95 v vddosc dc supply oscillator 1.65 1.95 v vddpll dc supply pll 1.65 1.95 v vddusb dc supply usb 1.65 1.95 v vddio dc supply peripheral i/os 3.0 3.6 v ref analog reference voltage 2.6 3.6 v il input low-level voltage -0.3 +0.8 v ih input high-level voltage 2.0 v vddio +0.3 v ol output low-level voltage 0.4 v oh output high-level voltage v vddio = v vddiom or v vddiop v vddio -0.4 i leak input leakage current pullup resistors disabled tbd c in input capacitance tqfp100 package tbd r pullup pull-up resistance tbd i o output current tbd i sc static current on v vddcore = 1.8v, cpu = 0 hz, cpu is in static mode t a =25c tbd all inputs driven; reset_n=1, cpu is in static mode t a =85c tbd
35 32058as?avr32?03/07 these figures represent the power consum ption measured on the power supplies. table 11-1. power consumption for different modes (1) mode conditions consumption unit active core/hsb clock is 66 mhz. pba clock is 30 mhz. pbb clock is 66 mhz. all peripheral clocks activated. measured while the processor is executing a recursive fibonacci algorithm. 40 ma table 11-2. power consumption by peripheral in active mode peripheral consumption unit gpio tbd ma usart tbd usbb tbd macb tbd smc tbd sdramc tbd adc tbd twi tbd pwm tbd spi tbd ssc tbd timer counter channels tbd
36 32058as?avr32?03/07 11.4 clock characteristics these parameters are given in the following conditions: ?v ddcore = 1.8v ?ambient temperature = 25c 11.4.1 cpu/hsb clock characteristics 11.4.2 pba clock characteristics 11.4.3 pbb clock characteristics 11.4.4 xin clock characteristics note: 1. these characteristics apply only wh en the main oscillator is in bypass mo de (i.e., when moscen = 0 and oscbypass = 1 in the ckgr_mor register.) table 11-3. core clock waveform parameters symbol parameter conditions min max units 1/(t cpcpu ) cpu clock frequency 66 mhz t cpcpu cpu clock period 15,15 ns table 11-4. pba clock waveform parameters symbol parameter conditions min max units 1/(t cppba ) pba clock frequency 33 mhz t cppba pba clock period 30,30 ns table 11-5. pbb clock waveform parameters symbol parameter conditions min max units 1/(t cppbb ) pbb clock frequency 66 mhz t cppbb pbb clock period 15,15 ns table 11-6. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 3 24 mhz t cpxin xin clock period 20.0 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance (1) tbd pf r in xin pulldown resistor (1) tbd k
37 32058as?avr32?03/07 11.5 crystal oscillat or characteristis the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power supply, unless otherwise specified. 11.5.1 32 khz oscillator characteristics note: 1. r s is the equivalent series resistance, c l is the equivalent load capacitance. 11.5.2 main oscillators characteristics notes: 1. c s is the shunt capacitance 11.5.3 pll characteristics note: 1. startup time depends on pll rc filter. a calculation tool is provided by atmel. table 11-7. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 hz duty cycle tbd tbd % t st startup time r s = tbd k , c l = tbd pf (1) tbd ms table 11-8. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 0.45 16 mhz c l1 , c l2 internal load capacitance (c l1 = c l2 ) tbd pf c l equivalent load capacitance tbd pf duty cycle tbd tbd tbd % t st startup time tbd ms i osc current consumption active mode @tbd mhz tbd a standby mode @tbd v tbd a table 11-9. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency 80 240 mhz f in input frequency tbd tbd mhz i pll current consumption active mode tbd ma standby mode tbd a
38 32058as?avr32?03/07 11.6 usb transceiver characteristics 11.6.1 electrical characteristics 11.6.2 switching characteristics table 11-10. electrical parameters symbol parameter conditions min typ max unit input levels v il low level tbd v v ih high level tbd v v di differential input sensivity |(d+) - (d-)| tbd v v cm differential input common mode range tbd tbd v c in transceiver capacitance capacitance to ground on each line tbd pf i hi-z state data line leakage 0v < v in < 3.3v tbd tbd a r ext recommended external usb series resistor in series with each usb pin with 5% tbd output levels v ol low level output measured with r l of 1.425 k tied to 3.6v tbd tbd v v oh high level output measured with r l of 14.25 k tied to gnd tbd tbd v v crs output signal crossover voltage measure conditions described in figure 11-1 tbd tbd v table 11-11. in low speed symbol parameter conditions min typ max unit t fr transition rise time c load = 400 pf tbd tbd ns t fe transition fall time c load = 400 pf tbd tbd ns t frfm rise/fall time matching c load = 400 pf tbd tbd % table 11-12. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf tbd tbd ns t fe transition fall time c load = 50 pf tbd tbd ns t frfm rise/fall time matching tbd tbd %
39 32058as?avr32?03/07 figure 11-1. usb data signal rise and fall times 11.7 ac characteristics - tbd 11.8 ebi timings - tbd
40 32058as?avr32?03/07
41 32058as?avr32?03/07 12. mechanical characteristics 12.1 thermal considerations 12.1.1 thermal data table 12-1 summarizes the thermal resistance data depending on the package. 12.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 12-1 on page 41 . ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 12-1 on page 41 . ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in the section ?power consumption? on page 34 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 12-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air tqfp100 tbd c/w jc junction-to-case thermal resistance tqfp100 tbd ja junction-to-ambient thermal resistance still air lqfp144 tbd c/w jc junction-to-case thermal resistance lqfp144 tbd t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
42 32058as?avr32?03/07 12.2 package drawings figure 12-1. tqfp-100 package drawing table 12-2. device and package maximum weight tbd mg table 12-3. package characteristics moisture sensitivity level tbd table 12-4. package reference jedec drawing reference ms-026 jesd97 classification e3
43 32058as?avr32?03/07 figure 12-2. lqfp-144 package drawing table 12-5. device and package maximum weight tbd mg table 12-6. package characteristics moisture sensitivity level tbd table 12-7. package reference jedec drawing reference ms-026 jesd97 classification e3
44 32058as?avr32?03/07 12.3 soldering profile table 12-8 gives the recommended soldering profile from j-std-20. note: it is recommended to apply a soldering temperature higher than 250c. a maximum of three reflow passes is allowed per component. table 12-8. soldering profile profile feature green package average ramp-up rate (217c to peak) tbd preheat temperature 175c 25c tbd temperature maintained above 217c tbd time within 5 c of actual peak temperature tbd peak temperature range tbd ramp-down rate tbd time 25 c to peak temperature tbd
45 32058as?avr32?03/07 13. ordering information 14. errata 14.1 rev. e 1. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 4. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 5. pwm channel status may be wrong if disabled before a period has elapsed before a pwm period has elapsed, the read channel status may be wrong. the chidx-bit for a pwm channel in the pwm enable register will read '1' fo r one full pwm period even if the channel was disabled before the period elapsed. it will then read '0' as expected. fix/workaround device ordering code package conditioning temperature operating range AT32UC3A0512 AT32UC3A0512-alut 144 lead lqfp tray industrial (-40 c to 85 c) at32uc3a1512 at32uc3a1512-aut 100 lead tqfp tray industrial (-40 c to 85 c) at32uc3a0256 at32uc3a0256-alut 144 lead lqfp tray industrial (-40 c to 85 c) at32uc3a1256 at32uc3a1256-aut 100 lead tqfp tray industrial (-40 c to 85 c) at32uc3a0128 at32uc3a0128-alut 100 lead tqfp tray industrial (-40 c to 85 c) at32uc3a1128 at32uc3a1128-aut 100 lead tqfp tray industrial (-40 c to 85 c)
46 32058as?avr32?03/07 reading the pwm channel status of a disabled channel is only correct after a pwm period has elapsed. 6. ssc does not trigger rf when data is low the ssc cannot transmit or receive data wh en cks = ckdiv and cko = none, in tcmr or rcmr respectively. fix/workaround set cko to a value that is not "none" and bypass the output of the tk/rk pin with the pio. 7. ssc data is not sent unless clock is set as output the ssc cannot transmit or receive data wh en cks = ckdiv and cko = none, in tcmr or rcmr respectively. fix/workaround set cko to a value that is not "none" and bypass the output of the tk/rk pin with the pio. 8. usb no end of host reset signaled upon disconnection in host mode, in case of an unexpected devic e disconnection whereas a usb reset is being sent by the usb controller, the uhcon.reset bi t may not been clear ed by the hardware at the end of the reset. fix/workaround a software workaround consists in testing (by polling or interrupt ) the disconnection (uhint.ddisci == 1) while waiting for the end of reset (uhcon.reset == 0) to avoid being stuck. 9. incorrect processor id the processor id reads 0x01 and not 0x02 as it should. fix/workaround none. 10. bus error should be masked in debug mode if a bus error occurs during debug mode, the processor will not respond to debug com- mands through the dinst register. fix/workaround a reset of the device will make the cp u respond to debug commands again. 11. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 12. read modify write (rmw) instructions on data outside the internal ram does not work. read modify write (rmw) instructions on da ta outside the internal ram does not work. fix/workaround do not perform rmw instructions on data outside the internal ram.
47 32058as?avr32?03/07 13. usart manchester encoder not working manchester encoding/decoding is not working. fix/workaround do not use manchester encoding. 14. usart rxbreak problem when no timeguard in asynchronous mode the rxbreak flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. fix/workaround if the nbstop is 1, timeguard should be different from 0. 15 usart handshaking: 2 characters sent / cts rises when tx if cts switches from 0 to 1 during the tx of a character, if the holding register is not empty, the txholding is also transmitted. fix/workaround none. 16. usart pdc and timeguard not supported in manchester manchester encoding/decoding is not working. fix/workaround do not use manchester encoding. 17. voltage regulator input and output is connected to vddio and vddcore inside the device the voltage regulator input and output is connected to vddio and vddcore respectively inside the device. fix/workaround do not supply vddcore externally, as this s upply will work in paralell with the regulator. 18. adc possible miss on drdy when disabling a channel the adc does not work properly when more than one channel is enabled. fix/workaround do not use the adc with more than one channel enabled at a time. 19. adc ovre flag sometimes not reset on status register read the ovre flag does not clear properly if read simultaneously to an end of conversion. fix/workaround none. 20. crc calculation of a locked device will calculate crc for 512 kb of flash memory, even though the part has less flash. fix/workaround the flash address space is wrap ping, so it is possible to use the crc value by calculating crc of the flash content concatenated with itself n times. where n is 512 kb/flash size. 21. sdram sdcke rise at the same time as sdck while exiti ng self-refresh mode
48 32058as?avr32?03/07 sdcke rise at the same time as s dck while exiting self-refresh mode. fix/workaround none. 22. pcx pins go low in stop mode in sleep mode stop all pcx pi ns will be controlled by gpio module instead of oscillators. this can cause drive contention on the xinx in worst case. fix/workaround before entering stop mode set all pcx pins to input and gpio controlled. 23. need two nops instruction after instructions masking interrupts the instructions following in the pipeline the instruction masking the interrupt through sr may behave abnormally. fix/workaround place two nops instructions after each ssrf or mtsr instruction setting ixm or gm in sr.
49 32058as?avr32?03/07 15. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 15.1 rev. a 03/07 1. initial revision.
i 32058as?avr32?03/07 1 description ............ .............. .............. ............... .............. .............. ............ 2 2 configuration summary ........ .............. .............. .............. .............. .......... 3 3 blockdiagram ............. ................ ................. ................ ................. ............ 4 3.1processor and architecture .......................................................................................5 4 signals description ............ .............. ............... .............. .............. ............ 7 5 package and pinout ................. ................ ................. ................ ............. 12 6 power considerations ........ .............. ............... .............. .............. .......... 15 6.1power supplies .......................................................................................................15 6.2voltage regulator ....................................................................................................15 7 i/o line considerations ...... .............. ............... .............. .............. .......... 16 7.1jtag pins ................................................................................................................16 7.2reset_n pin ............ ................. ................ ................ ................ ................ .............16 7.3twi pins ..................................................................................................................1 6 7.4gpio pins ................................................................................................................16 8 memories ............... .............. .............. ............... .............. .............. .......... 17 8.1embedded memories ..............................................................................................17 8.2physical memory map .............................................................................................17 9 peripherals ............ .............. .............. ............... .............. .............. .......... 19 9.1peripheral address map ..........................................................................................19 9.2interrupt request signal map ..................................................................................20 9.3clock connections ..................................................................................................23 9.4nexus ocd aux port connections .........................................................................23 9.5dma handshake signals ..........................................................................................24 9.6peripheral multiplexing on i/o lines .........................................................................25 9.7oscillator pinout ......................................................................................................28 9.8peripheral overview .................................................................................................28 10 boot sequence ........... ................ ................. ................ ................. .......... 32 10.1starting of clocks ...................................................................................................32 10.2fetching of initial instructions ................................................................................32 11 electrical characteristics ... .............. ............... .............. .............. .......... 33 11.1absolute maximum ratings* .................................................................................33 11.2dc characteristics ................................................................................................34 11.3power consumption ..............................................................................................34
11.4clock characteristics .............................................................................................36 11.5crystal oscillator characteristis ............................................................................37 11.6usb transceiver characteristics ...........................................................................38 11.7ac characteristics - tbd ......................................................................................39 11.8ebi timings - tbd .................................................................................................39 12 mechanical characteristics ..... ................ ................. ................ ............. 41 12.1thermal considerations ........................................................................................41 12.2package drawings ................................................................................................42 12.3soldering profile ....................................................................................................44 13 ordering information .......... .............. ............... .............. .............. .......... 45 14 errata ............. ................ ................. ................ ................. .............. .......... 45 14.1rev. e .................................................................................................................... 45 15 datasheet revision history .. .............. .............. .............. .............. ........ 49 15.1rev. a 03/07 ..........................................................................................................49
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